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CY3148
Cypress Cadence Bolt-in Kit
Features
* Seamless integration with your Cadence ConceptTM and simulation tools * Supports pre-synthesis simulation using LeapfrogTM * Powerful schematic symbol library * IEEE-compliant VHDL * Supports the full UltraLogicTM family of SPLDs and CPLDs * Industry-leading synthesis for programmable logic * 100% automatic fitting * VHDL and Verilog post-layout timing models * Complete solution from design entry to programming Programming
Warp generates JEDEC programming files for all Cypress devices which can be used for in-system reprogramming (ISRTM) or with various device programmers.
System Requirements
For Sun Workstations SPARC CPU SunOS 4.1.3 or Solaris 2.5 CD-ROM drive
Ordering Information
CY3148 Cypress Cadence Bolt-in Kit includes: CD-ROM with Bolt-in software and on-line documentation CD-ROM with Warp software and on-line documentation Warp User's Guide and Reference Manual Release Notes VHDL for Programmable Logic Textbook
Introduction
Cypress offers powerful integrated solutions for programmable logic. The Cypress Cadence Bolt-in Kit gives you everything to design with Cypress's UltraLogic PLDs in one seamless device-independent design environment. It allows you to take advantage of Cadence's powerful ConceptTM schematic entry tool, Cypress's industry-leading WarpTM VHDL synthesis tool, and a wide variety of simulators.
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Functional Description Design Flow Manager
Design Entry and Pre-Synthesis Simulation Design with ease using schematic symbols, VHDL, or a combination of both, supported with Cadence's Concept tool available with your Cadence flow. Prior to synthesis, you can use LeapfrogTM to verify your functionality. Synthesis Your entire design is automatically converted into VHDL and efficiently synthesized into a SPLD or CPLD device using Warp. UltraGenTM synthesis technology will ensure that you achieve the best results for every Cypress device. For a description of UltraGen and synthesis, see the Warp datasheets. Fitting Easily retarget your design to different devices. The 100% automatic fitting tools produce optimal results in minutes. Post-Synthesis Simulation
Simulation Synthesis
Fitting
Program File
Device Sim
Warp outputs VHDL and Verilog timing simulation models. Verify your design with timing using your choice of Cadence's LeapfrogTM VHDL or Verilog-XLTM simulators or any other VHDL or Verilog simulator.
Document #: 38-00681-B
Available from Cypress Available from Cadence
Figure 1. Cypress Cadence Design Flow
SunOS and Solaris are trademarks of Sun Microsystems Corporation. Concept, Leapfrog, and Verilog-XL are trademarks of Cadence Design System, Inc. ISR, UltraGen, UltraLogic, and Warp are trademarks of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation
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3901 North First Street
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San Jose * CA 95134 * 408-943-2600 November 26, 1997 - Revised April 13, 1998

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